Virtex-7 FPGA Gen3 integrated module Completion timeout mechanism

With any split transaction protocol there is a risk that Requesters will not get the desired Completion. To allow Requesters to use a standard way to recover from this situation, the Completion timeout mechanism is specified.

The PCIE specification stipulates that PCIE devices that issue Requests that require Completions must implement the Completion Timeout mechanism. With the exception of Configuration Requests. The Completion timeout mechanism is activated every time a PCIE device sends a Requests that require Completions. PCIE Root Complexes, PCI Express-PCI Bridges, and Endpoints need to implement the Completion timeout mechanism. Switches do not need to actively initiate operations, so there is no need for Completion timeout.

Completion timeout can be disabled by configuration software. The Completion Timeout is disabled by bit 4 of the configuration register Device Control 2.

Virtex-7 FPGA Gen3 integrated module Completion timeout mechanism

figure 1

In the Gen3 Integrated Block of V7, there are some special places in the implementation of Completion Timeout, which need to be paid attention to when applying.

First, configure the bit of Device Control 2 of the register[3:0]The value of Completion timeout is specified, and bit4 controls the disable of Completion timeout. This part is consistent with the specification.

Virtex-7 FPGA Gen3 integrated module Completion timeout mechanism

figure 2

In addition, in the properties of Gen3 Integrated Block, there are some properties related to Completion timeout.The first is PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE, this propertyControls whether Completion timeout is allowed to be disabled. By default this property is set to FALSE.If you need to modify this property, you need toModified in the verilog/VHLD code.

Virtex-7 FPGA Gen3 integrated module Completion timeout mechanism

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Secondly, there are two attributes TL_COMPL_TIMEOUT_REG0/1, which control the value of timeout.These two propertiesCorresponding to the bit of the vice Control 2 respectively[3:0]Set to the case of 0101 and 0110.Under these two settings, the value of timeout is controlled by these two properties. Again, these two properties can also be modified by the relevant verilog/VHLD code.

Virtex-7 FPGA Gen3 integrated module Completion timeout mechanism

Figure 4

In fact, although the bit of Device Control 2[3:0]9 timeout values ​​are defined, only bit3[3:0]When set to 0101 and 0110,The Completion timeout mechanism of the Gen3 Integrated Block can only work. When set to other values, the Completion timeout mechanism does not work. Special attention should be paid to this point. If a timeout mechanism is required, the bit of Device Control 2 must be set.[3:0]Set to one of these two values.

When a timeout occurs, on the Requester Completion bus, the bit of the completion[15:12]Will be set to 1001, indicating that tim appearseout. At this time, Completion has only bit 30 (request Completed bit), bits [71: 64] (tag field) and bits [55: 48](requester Function field) is valid.

Virtex-7 FPGA Gen3 integrated module Completion timeout mechanism

Figure 5

The following figure is a simulated TIMEOUT waveform, setting the bit of Device Control 2[3:0]is 0x5, set PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE toFALSE, set TL_COMPL_TIMEOUT_REG0/1 to 0x1 (in order to shorten the simulation time). when Requester did not get the Completion, after timeout, you can see that 1001 Er appeared on the RC busror code.

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