With any split transaction protocol there is a risk that Requesters will not get the desired Completion. To allow Requesters to use a standard way to recover from this situation, the Completion timeout mechanism is specified.
The PCIE specification stipulates that PCIE devices that issue Requests that require Completions must implement the Completion Timeout mechanism. With the exception of Configuration Requests. The Completion timeout mechanism is activated every time a PCIE device sends a Requests that require Completions. PCIE Root Complexes, PCI Express-PCI Bridges, and Endpoints need to implement the Completion timeout mechanism. Switches do not need to actively initiate operations, so there is no need for Completion timeout.
Completion timeout can be disabled by configuration software. The Completion Timeout is disabled by bit 4 of the configuration register Device Control 2.
In the Gen3 Integrated Block of V7, there are some special places in the implementation of Completion Timeout, which need to be paid attention to when applying.
First, configure the bit of Device Control 2 of the register[3:0]The value of Completion timeout is specified, and bit4 controls the disable of Completion timeout. This part is consistent with the specification.
In addition, in the properties of Gen3 Integrated Block, there are some properties related to Completion timeout.The first is PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE, this property
Secondly, there are two attributes TL_COMPL_TIMEOUT_REG0/1, which control the value of timeout.These two properties
In fact, although the bit of Device Control 2[3:0]9 timeout values are defined, only bit3[3:0]When set to 0101 and 0110,
When a timeout occurs, on the Requester Completion bus, the bit of the completion[15:12]Will be set to 1001, indicating that tim appears
The following figure is a simulated TIMEOUT waveform, setting the bit of Device Control 2[3:0]is 0x5, set PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE to