ALTERA company Bai Hailong Chen Wen
QDR2 RAM is a special structure of SRAM, its read and write ports are separate, there are two sets of read and write data bus. The address is shared by read and write. For the QDR2 RAM with a BURST length of 2, the read address is latched on the upper edge of the clock CK, and the write address is latched on the lower edge of the clock CK. Its structure eliminates the need for a turn-around of the data bus, resulting in lower latency.
In ALTERA’s high-end FPGA, we can use some low-level IP, such as DQDQS, DLL, PLL to implement a low-latency QDR2 RAM read-write controller, because of its simple structure and small read delay, it can meet customers’ needs in some data communication Product requirements, such as frame header access.
Figure 1 Structure diagram of the controller
Figure 2 Read latency is 7 clock cycles
FPGA implementation scheme
The structure of this controller is shown in Figure 1, including a DLL, a group of DQDQS, a PLL, command address output module, data input reception and synchronization module. PLL generates internal data clock and command clock, DLL and DQDQS are responsible for phase-shifting DQS, converting 36-bit double-edge input data into 72-bit single-edge parallel data, command address output module generates read and write addresses, read and write command signals, data input and receive And the synchronization module is responsible for synchronizing the data received by DQDQS to the internal data clock domain.
The internal user interface of this controller includes 21-bit read and write address input, 72-bit input data, 72-bit output data, single-bit read enable and write enable control, and single-bit read data valid signal. All of these signals are synchronized to the data clock domain of the PLL for user convenience. The QDR2 RAM interface is a standard form, 36bit output data, 36bit input data, a pair of DQS differential pairs, a pair of output clock CK differential pairs, and read and write control signals.
Table 1 FPGA resources consumed by the controller
FPGA Design Resources and Performance
The FPGA resources consumed by this controller are shown in Table 1 (implemented on an A2GZ device).
The read delay (from the rising edge of the read request signal qdr2_rps_en_n to the rising edge of the return data valid signal clt_rd_valid) is 7 clock cycles, as shown in Figure 2.
This design can be ported to all mid-to-high-end FPGAs of ALTERA, including A2GX, A2GZ, STRATIX3, STRATIX4, and STRATIX5, and has no impact on performance such as latency.
The Links: EPM240M100C4N DMF-50260NFU-FW-23