“Currently, high-precision A/D conversion and real-time processing are increasingly required in many fields. At the same time, the market demands to support more complex Display and communication interfaces are also increasing, such as environmental monitoring, electricity meters, medical equipment, portable data acquisition, and industrial sensors and industrial controls. The traditional design method is to use MCU or DSP to control the A/D conversion of data acquisition through software, which will frequently interrupt the operation of the system, thereby weakening the data computing capability of the system and limiting the speed of data acquisition.In this paper, the DSP+FPGA scheme is adopted, and the A/D conversion and data storage are controlled by hardware to maximize the reliability of the system.
Currently, high-precision A/D conversion and real-time processing are increasingly required in many fields. At the same time, the market demands to support more complex display and communication interfaces are also increasing, such as environmental monitoring, electricity meters, medical equipment, portable data acquisition, and industrial sensors and industrial controls. The traditional design method is to use MCU or DSP to control the A/D conversion of data acquisition through software, which will frequently interrupt the operation of the system, thereby weakening the data computing capability of the system and limiting the speed of data acquisition. In this paper, the scheme of DSP+FPGA is used, and the A/D conversion and data storage are controlled by hardware, so as to maximize the signal acquisition and processing capability of the system.
The whole acquisition card includes signal conditioning, data acquisition, data processing and bus interface design. The system structure is shown in Figure 1.
Figure 1 System structure block diagram
In this paper, a signal conditioning circuit with functions of signal attenuation, gain amplification and filtering is designed. The AD7676 A/D converter with 16-bit precision and a maximum sampling rate of 500KSPS is used. The digital system design uses the extremely flexible and programmable characteristics of FPGA. Altera’s FPGA chip EP2C8Q208 completes precision correction and logic timing control; DSP uses TI’s TMS320VC5416, so that the A/D-converted data is processed, marked, packaged and pre-processed before being transmitted to the host computer. The data acquisition card can perform 8-channel data acquisition at the same time, and the channels can be set for attenuation multiple, sampling speed and amplification gain. It also provides analog output channels for waveform generation and analog drive functions. Automatic calibration can be performed to ensure the accuracy of data collection. The PCI bus interface circuit adopts the PCI bus interface chip PCI9030 of PLX Technology Company to complete data acquisition and transmission of status and control signals.
System hardware circuit design
Design of Data Acquisition Module
The 8-channel analog input signals sent from the sensor are selected to enter the analog channel through the multi-channel analog switch ADG507. If multiple channels are collected at the same time, the time division multiplexing method is adopted, and the FPGA controls the on-off of each channel in turn. The mode selection switch ADG509 is a four-to-one analog switch, which can select the analog signal under test, the standard reference voltage value or the signal converted by the DAC for channel calibration and enter the post-stage filter attenuation network circuit. The signal sent to the ADC is first low-pass filtered to filter out high-frequency noise. The filter circuit is designed as a second-order resistance-capacitance low-pass filter, which filters signals with a frequency higher than 50KHz. The attenuation circuit is designed as active attenuation. The differential amplifier LTC1992 from Linear Company is used to complete the polarity conversion of the input signal, and realize the conversion of single-ended signal to differential signal. Adjustment of signals with different voltage input ranges to meet the input voltage range of the AD7676. The signal gain programmable amplifier LTC6911 can be programmed to set the gain multiple of 1 V/V~100 V/V in steps of 1, 2, and 5. During the data acquisition process, the gain multiple of the gain amplifier is automatically adjusted by the comparison circuit inside the FPGA. The ability to distinguish weak signals is greatly improved. AD7676 is a differential signal input. The MAX6325 reference source provides a reference voltage of 2.5V. The sampling clock is obtained by the crystal oscillator providing a 10MHz clock signal through the internal frequency division circuit of the FPGA. The maximum sampling rate of a single channel is 500KSPS.
FPGA circuit design
FPGA chip is also a special ASIC chip, which belongs to programmable logic device. It is developed on the basis of logic devices such as PAL and GAL. Compared with the previous PAL, GAL, etc., the FPGA scale is relatively large, and is suitable for logic circuit applications such as timing and combination. This text selects the FPGA chip EP2C8Q208 of Altera Company to complete the sequence and address decoding circuit design of the data acquisition card. Since EP2C8Q208 has 36 M4K RAMs, a 16-bit width and 4KB depth FIFO is designed inside the FPGA, and the FIFO is used to improve the data acquisition card’s ability to collect and store multi-channel signals. The FIFO has half-full, full, and empty flag bits. When the DSP detects the half-full flag bit, the FIFO reads and writes at the same time; when it is full, it reads only and does not write; when it is empty, it only writes and does not read. The A/D sampling control signal is controlled by the DSP through the FPGA; the DSP further processes the collected data to improve the accuracy, and also has the functions of a traditional CPU or MCU to handle timing, triggering, and DMA interrupt requests accordingly.
DSP circuit design
The DSP adopts TMS320VC5416, which is a 16-bit fixed-point DSP with high operational flexibility and high running speed. It adopts an improved Harvard structure (1 set of program memory bus, 3 sets of data memory bus, 4 sets of address bus), with dedicated Hardware logic CPU, on-chip 128KB memory, on-chip peripherals, and a highly efficient instruction set.
The role of DSP in the system is mainly to organize, mark, pack and pre-process the data after A/D conversion before it is transmitted to the host computer. All the control signals of the data acquisition system are generated by the DSP controlled FPGA logic circuit. DSP plug-in Flash stores DSP programs and other configuration data. When powered on, DSP uses parallel mode to transfer into DSP for internal execution.
Calibration Circuit Design
The calibration circuit is an important part of this design. The high-precision performance of the data acquisition card depends not only on the high-resolution ADC, but also on the excellent self-calibration and anti-noise capabilities of the data acquisition card to a greater extent.
During calibration, the DSP sends out the standard value. After D/A and A/D conversion, the collected data value is compared with the original standard value, and its deviation coefficient is used to form a denoising equation to realize the self-calibration of the data acquisition card.
PCI bus interface circuit design
The PCI bus specification is very complex, and the realization of its interface is difficult. The data acquisition card uses PCI9030 as the user interface, which provides a simple method for the development of the PCI bus interface. It only needs to design a simple local bus interface control circuit to realize the high-speed data transmission of the PCI bus. The use of Altera’s Quartus II enables the hardware to realize software design, updates the traditional circuit design and debugging methods, and greatly shortens the development cycle. In particular, its design simulation and timing analysis make the design more reliable and ensure the correctness of the system.
System software design
In the Windows98/ 2000/ XP environment, the application program in Windows user mode cannot directly operate the hardware device. To achieve access to the hardware resources (such as memory, interrupt, etc.) device driver. At present, the most used development tool is WinDriver, the driver development component of GUNGO. The use of WinDriver to develop drivers does not need to be familiar with the kernel knowledge of the operating system. All functions in the entire driver program work in user mode, and achieve the purpose of driving hardware by interacting with WinDriver’s .VXD and .SYS files. Because the WinDriver development environment provides modules such as memory range, registers and interrupt processing for PLX’s Chips, this paper adopts the WinDriver5.3 development tool of GUNGO, which supports the PCI interface chips of PLX, and users do not need to have DDK and core state. Program development experience, can be combined with PLX company’s PLXmon tool when debugging.
Operation interface design
The interface is designed using LabVIEW software from National Instruments. LabVIEW is a graphical programming language. The operation interface simulates the control panel of the actual instrument, enabling users to complete functions such as channel selection, mode selection, gain setting, sampling rate setting, etc. The operation is simple and convenient.
System Indicator Analysis
ADC Error Analysis
Commonly used ADCs mainly have quantization errors, gain errors and offset errors. The quantization error exists in any ADC and can only be reduced by increasing the ADC resolution. In order to reduce the quantization error to ±1LSB/2, the usual method is to shift the transform characteristic by 1LSB/2. Offset error is the difference between the actual code and the ideal code when using a zero-volt differential input to the ADC.Gain error is the transition from negative full scale to
The difference between the actual slope and the ideal slope for a positive full-scale input. Offset and gain errors are often the dominant error sources in ADCs. For offset calibration, this article takes a 0V or very small signal and reads the output code. If the result is positive, the converter has a positive offset error and the offset value is subtracted from the result; if the result is negative, the converter has a negative offset error and the offset value can be added to the result. Gain calibration is accomplished by applying a full-scale or near-full-scale signal to the ADC and measuring the output code. Offset calibration is performed before gain calibration.
Analog Switch Error Analysis
Multiplexers can be broadly classified into two types, analog Electronic switches and mechanical contact switches. The analog switch has the advantages of fast conversion speed, long service life, small size, low cost, high integration and no jitter; but there are also some disadvantages, such as large on-resistance, inter-channel interference, and common ground between channels.
The data acquisition card designed in this paper uses ADI’s ADG507 and ADG509, the on-resistance Ron100~300Ω, the input signal should be divided by Ron, and the output voltage to the load resistance should drop a little. For this reason, this design uses OPA2277 as a voltage level follower and connects it to the load circuit behind to pull up the load impedance of the multi-channel analog switch and weaken the influence of the series internal resistance.
The data acquisition card uses the programmable gain amplifier LTC6911, and the maximum adjustable gain is 100 V/V, which greatly improves the ability of the acquisition card to distinguish weak signals. At the same time, the resistance attenuation network of the signal conditioning part can complete the 1/2 and 1/4 voltage division of the signal, which expands the dynamic range of the data acquisition card. Signal and interference noise are mixed together in the time domain, but have different characteristics in the frequency domain. Therefore, pre-design filters to suppress the noise signal to avoid high noise levels. Receiving such a signal with a gain amplifier will cause the amplifier to saturate. make the instrument not work properly.
The voltage reference source is an important part of the A/D or D/A conversion circuit, and the system output accuracy largely depends on the accuracy of the voltage reference source. Here mainly consider the output accuracy, stability and temperature drift coefficient. The MAX6325 is a low-noise, high-precision buried Zener voltage reference chip with an initial output voltage accuracy of 0.02% and a temperature coefficient of 0.5ppm/°C.
The data acquisition card adopts 16-bit precision ADC. The analog signal channel design considers weak signal detection, noise suppression, high-frequency filtering, differential amplifier circuit and programmable gain amplifier circuit. The digital circuit part is designed with EP2C8Q208 as the core, and the timing sequence of FPGA is strictly used. , fast speed, good programmability and other characteristics, introduce various control and status signals that may be required into FPGA, and use the large capacity and field programmable characteristics of FPGA to make field modifications according to different requirements, which increases the system design. success rate and flexibility. At the same time, the preprocessing of the data by DSP greatly improves the accuracy of the data. Filtering, grounding and reasonable signal routing are carefully considered during PCB wiring, which improves the reliability of the data acquisition card.
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